This disclosure relates to high voltage clamps for integrated circuits. The need for protection against electrostatic discharge (ESD) exists, for example, in applications including programming pads. Such applications may involve One Time Programmable (OTP) memories used in RFID, video game consoles, mobile phones, and the like.
Design of high voltage tolerant ESD clamps using nominal devices can be quite challenging. During programming mode, the use of simple ESD clamps using nominal devices often present reliability issues such as gate oxide stress, drain/well voltage overstress, etc. A commonly used technique to overcome such problems is by stacking nmos FETs in a clamping device. An example of such technique is disclosed in U.S. Pat. No. 7,203,045. Multilevel stacking of nmos elements, however, reduces clamping efficiency with each added level. Reliability concerns exist with respect to drain junction voltages and gate oxide breakdown, as well as the possibility of leakage currents during normal functioning modes.
A high voltage tolerant clamp is needed that uses nominal devices, yet avoids reliability stress that can occur due to a high voltage application. Such clamp should be optimized to reduce area and current leakage.